High-speed base-band transmission systems (5 Gbit/s or more) that are used in chip-to-chip, wire-line or fiber communications often include a serializer-deserializer (SERDES) block. A SERDES block converts bits carried over a parallel bus into a serial bit stream for transmission over the communication channel that can also include board traces, back-planes, connectors etc. On the receive side, the detected serial bits are converted back to the parallel stream.
The transmitter sends the data bits in one of a variety of different formats, such as for example nor-return-to-zero (NRZ) modulation or pulse amplitude modulation (PAM). Examples of SERDES applications can be found in different high-speed interface protocols such as PCI Express, SAS/SATA etc.
A variety of physical impairments limit the effective high-speed transmission of data signals, such as the frequency selective nature of the channels, which causes different frequency components of the input signal to be attenuated and phase-shifted differently. This causes the impulse response to span several symbol intervals, resulting in time-smearing and interference between successive transmitted input symbols, commonly known as intersymbol interference (ISI). The ISI resulting from the channel distortion, if left uncompensated, causes high error rates. The solution to the ISI problem is to design a receiver that employs a means for compensating or reducing the ISI in the received signal. The compensator for the ISI is called an equalizer and it is often included into the SERDES receiver design.
Two very popular equalizer structures used to mitigate the ISI are a linear equalizer (LE) and a decision feedback equalizer (DFE). In contrast to the maximum likelihood sequence estimation (MSLE), the data detection in LE and DFE is done on a symbol-by-symbol basis and hence it is much simpler to implement. However, the price is in the sub-optimality from a bit error rate (BER) perspective.
The equalizer implementation can be done in analog or digital circuitry, or combination of both techniques. The advantages of digital implementation are in design flexibility, but usually at the expense of more power requirements. The analog implementations are less power hungry and they can operate at faster clock rates.
When the final SERDES system is validated, it is assessed in terms of its tolerance to sinusoidal jitter (SJ) under various operating conditions. This is a characterization based on the BER of the received signal.
Improvements to methods and systems for measuring the signal and to provide insight in the impairments of the received and recovered signal are desired.